- – Typically requires at least 5+ years experience in Semiconductor Packaging Design, Process and New Product Introduction.
- – Strong knowledge and R&D experience in IC packaging, SIP Module packaging, single die packaging and heterogeneous package integration.
- – Hands on experience in various wafer level, package level assembly process, materials, and equipment
- – Strong IC packaging materials background including characterization and failure analysis.
- – Problem solver with strong engineering physics. Willing to tackle tough problems.
- – Ability to work independently and work with multi-functional teams.
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